A New Hybrid Asymmetric Multilevel Inverter with Reduced Number Of Switches

被引：0
|
作者：
Prabaharan, N. [1 ]
Palanisamy, K. [1 ]
机构：
[1] VIT Univ, Sch Elect Engn, Vellore, Tamil Nadu, India
来源：
2016 IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, DRIVES AND ENERGY SYSTEMS (PEDES) | 2016年
关键词：
multilevel inverter; pulse width modulation; reduced switch MLI; asymmetric; total harmonic distortion; TOPOLOGIES; VOLTAGE;
D O I：
暂无
中图分类号：
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号：
0807 ; 0820 ;
摘要：
This paper proposes a new hybrid asymmetric multilevel inverter for generating the higher number of levels with reduced number of power semiconductor switches. The hybrid asymmetric multilevel inverter consists of full bridge inverter and reduced switch inverter topology. The reduced switch inverter topology can generate 13-level output voltage without utilizing full bridge inverter. When the full bridge inverter is combined with reduced switch inverter topology, it can generate the 27-level output voltage. Sinusoidal pulse width modulation technique is used to trigger the multilevel inverter switches and to achieve high-quality output voltage with lesser total harmonic distortion. The performance of proposed multilevel inverter is tested by MATLAB/SIMULINK and validated the results with different parameters. The output voltage level of proposed multilevel inverter is satisfied IEEE519 harmonic standard without using any passive filters.
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页数：4
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