Analysis of edge placement error (EPE) at the 5nm node and beyond

The resolution concept of kl is introduced along with various methods to reduce the kl through resolution enhancement techniques. The edge placement error (EPE) of a 5nm node SRAM is analyzed in detail for aligning a via 0 (V0) layer to the metal 0 (M0) layer. These layers arc optimized with source mask optimization (SMO), and the EPE is minimized from stochastics, global critical dimension uniformity (CDU), overlay, optical proximity correction (OPC) error, and scanner matching error. The largest source of error in EPE is from stochastic EPE (SEPE) in which 5nm of maximum EPE is produced. Since SEPE is difficult to reduce, more emphasis needs to be placed on reducing the overlay EPE in order to reduce the total EPE.