Characterization of a Capacitorless DRAM Cell for Cryogenic Memory Applications

被引:21
作者
Bae, Jong-Ho [1 ,2 ,3 ]
Back, Jong-Won [1 ,2 ]
Kwon, Min-Woo [1 ,2 ]
Seo, Jae Hwa [1 ,2 ]
Yoo, Keon [1 ,2 ]
Woo, Sung Yun [1 ,2 ]
Park, Kyungchul [1 ,2 ]
Park, Byung-Gook [1 ,2 ]
Lee, Jong-Ho [1 ,2 ]
机构
[1] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 08826, South Korea
[2] Seoul Natl Univ, ISRC, Seoul 08826, South Korea
[3] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
基金
新加坡国家研究基金会;
关键词
Capacitor-less DRAM; 1T-DRAM; PDSOI; MOSFET; cryogenic memory; QUANTUM; OPERATION; QUBIT;
D O I
10.1109/LED.2019.2933504
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell. In the Shockley-Read-Hall theory, the generation-recombination rate decreases with decreasing temperature, therefore, the retention properties of the capacitorless single transistor DRAM cell are greatly improved as temperature decreases. The static and dynamic retention times increase sharply as temperature decreases. The dynamic retention time reaches up to similar to 3.5 s at 80K, which is similar to 10(4) times larger than that at 300K. In addition, as the temperature decreases, the current sensing margin also increases more than 2.5 times at 80K (similar to 11 mu A) compared to that at 300K, due to the improved dynamic retention characteristics and the increased transconductance.
引用
收藏
页码:1614 / 1617
页数:4
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