Performance Enhancement in Multi Gate Tunneling Field Effect Transistors by Scaling the Fin-Width

被引:81
作者
Leonelli, Daniele [1 ,2 ]
Vandooren, Anne [1 ]
Rooyackers, Rita [1 ]
Verhulst, Anne S. [1 ,2 ]
De Gendt, Stefan [1 ,3 ]
Heyns, Marc M. [1 ,4 ]
Groeseneken, Guido [1 ,2 ]
机构
[1] IMEC, B-3001 Louvain, Belgium
[2] Katholieke Univ Leuven, ESAT, Dept Elect Engn, B-3001 Louvain, Belgium
[3] Katholieke Univ Leuven, Dept Chem, B-3001 Louvain, Belgium
[4] Katholieke Univ Leuven, Dept Met & Mat Engn, B-3001 Louvain, Belgium
关键词
SILICON; IMPACT; FET; DEVICE; BULK;
D O I
10.1143/JJAP.49.04DC10
中图分类号
O59 [应用物理学];
学科分类号
摘要
This paper discusses the electrical characterization of complementary multiple-gate tunneling field effect transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard complementary metal oxide semiconductor (CMOS) processing, emphasizing the dependence of the tunneling current on the fin-width. A linear dependence of the tunneling current for narrow fins with the square root of the fin width is experimentally reported for the first time. The comparison between narrow fins and planar-like fins offers additional insights about the fin-width dependence. The output characteristic shows a perfect saturation, very attractive for analog circuits. The temperature dependence is measured indicating a weak dependence as expected for tunneling devices. Measured devices with a point slope of 46 mV/dec at low biases and an I-on/I-off ratio of 106 at a supply voltage of 1.2 V for 25 nm wide fins are reported as best performing devices with a MuGFET technology using a high-k dielectric and a metal gate inserted gate stack. (C) 2010 The Japan Society of Applied Physics
引用
收藏
页数:5
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