Overstress and electrostatic discharge in CMOS and BCD integrated circuits

被引：9

作者：

Meneghesso, G

Ciappa, M

Malberti, P

Sponton, L

Croce, G

Contiero, C

Zanoni, E

机构：

[1] Univ Padua, Dipartimento Elettron & Informat, I-35131 Padua, Italy

[2] INFM, Sez Padova, I-35131 Padua, Italy

[3] ETH Zentrum, Integrated Syst Lab, CH-8092 Zurich, Switzerland

[4] ST Microelect, Dedicated Prod Grp, I-20010 Milan, Italy

来源：

MICROELECTRONICS RELIABILITY | 2000年 / 40卷 / 8-10期

关键词：

D O I：

10.1016/S0026-2714(00)00190-6

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The ESD qualification of the new technologies is obtained by testing different device structures an comparing the ESD robustness evaluated by means of different testing methods (HBM, MM, CDM and TLP). The influence of the layout parameters on the ESD robustness must also be characterized. In this paper we will present data concerning the ESD robustness of both 0.35 mu m CMOS and 0.6 mu m smart power (BCD5) protection structures. A study of the influence of layout parameters on the ESD robustness with different test methods (HBM, CDM and TLP) will be given. Failure analysis by means of electrical characterization, Emission Microscopy and SEM inspection will also been presented. (C) 2000 Elsevier Science Ltd. All rights reserved.

引用

页码：1739 / 1746

页数：8

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