Correlation between I-V Slope and TDDB Voltage Acceleration for Cu/Low-k Interconnects

被引：5

作者：

Chen, F. ^{[1
]}

Gambino, J. ^{[1
]}

Shinosky, M. ^{[1
]}

Li, B. ^{[1
]}

Bravo, O. ^{[1
]}

Angyal, M. ^{[1
]}

Badami, D. ^{[1
]}

Aitken, J. ^{[1
]}

机构：

[1] Semicond Solut, IBM Syst & Technol Grp, Essex Jct, VT 05452 USA

来源：

PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2009年

关键词：

D O I：

10.1109/IITC.2009.5090382

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a correlation between the IN slope at low fields and TDDB voltage acceleration is demonstrated for the first time, based on a wide range of data from 32nm to 130nm node hardware. The data supports the root E model, which is based on electron fluence (leakage current) driven, Cu catalyzed, low-k dielectric breakdown. Using this correlation, a fast wafer level screen method was also implemented for process improvement and TDDB reliability monitoring.

引用

页码：182 / 184

页数：3