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- [41] A Full-System Approach to Multi-Valued Logic Design 2024 IEEE 35TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, ASAP 2024, 2024, : 226 - 227
- [42] Complexity of Representations of Multiple-Output Boolean Functions in the Reversible Logic Circuits PROCEEDINGS OF THE XIX IEEE INTERNATIONAL CONFERENCE ON SOFT COMPUTING AND MEASUREMENTS (SCM 2016), 2016, : 374 - 376
- [43] Multi-level factorisation technique for pass transistor logic IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1998, 145 (01): : 48 - 54
- [44] Design of submicrometer CMOS differential pass-transistor logic circuits IEEE Journal of Solid-State Circuits, 1991, 26 (09): : 1249 - 1258
- [46] Multi-input variable-threshold circuits for multi-valued logic functions 30TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2000, : 27 - 32
- [47] Generating digital circuits tests using multi-valued logic and inductive statements Engineering Simulation, 1997, 14 (01): : 75 - 82
- [48] Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits 40TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC ISMVL 2010, 2010, : 128 - 133
- [49] Multi-Valued Logic Based on Probability-Generated Aggregators 2014 IEEE 28TH CONVENTION OF ELECTRICAL & ELECTRONICS ENGINEERS IN ISRAEL (IEEEI), 2014,