A dynamic CAM - based on a one-hot-spot block code-for millions-entry lookup

被引：8

作者：

Hanzawa, S ^{[1
]}

Sakata, T ^{[1
]}

Kajigaya, K ^{[1
]}

Takemura, R ^{[1
]}

Kawahara, T ^{[1
]}

机构：

[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

10.1109/VLSIC.2004.1346623

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

With the aim of realizing large-scale and low-power CAMs for millions-entry lookup, the authors have devised a one-hot-spot block code and developed three circuit techniques. The proposed code efficiently stores IP addresses and reduces the entry count down by 52% on average. The first and second techniques, a hierarchical match-line structure and an on-chip entry compression/extraction scheme, enable the proposed code to be applied to our new CAM. In addition to the second technique, the third technique, a search-depth control scheme, restricts activating unneeded search lines and reduces power consumption down by 45%. In the case of 72-bit data, the proposed CAM, using a stacked capacitor, effectively achieves 1.5 million entries, which is six times larger than that of a conventional static TCAM.

引用

页码：382 / 385

页数：4

共 8 条

[1]

GUPTA P, 2001, IEEE NETWORK MAR, P24

[2] 200MHz/200MSPS 3.2W at 1.5V vdd, 9AMbits ternary CAM with new charge injection match detect circuits and bank selection scheme [J].

Kasai, G ;

Takarabe, Y ;

Furumi, K ;

Yoneda, M .

PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, :387-390

[3] 66MHz 2.3M ternary dynamic Content Addressable Memory [J].

Lines, V ;

Ahmed, A ;

Ma, P ;

Ma, S ;

McKenzie, R ;

Kim, HS ;

Mar, C .

RECORDS OF THE 2000 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING, 2000, :101-105

[4] A design for high-speed low-power CMOS fully parallel content-addressable memory macros [J].

Miyatake, H ;

Tanaka, M ;

Mori, Y .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (06) :956-968

[5] A cost-efficient dynamic Ternary CAM in 130nm CMOS technology with planar complementary capacitors and TSR architecture [J].

Noda, H ;

Inoue, K ;

Mattausch, HJ ;

Koide, T ;

Arimoto, K .

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, :83-84

[6]

PAGIAMTZIS K, 2003, CICC P, P383

[7]

YAMADA H, 1987, ISSCC FEB, P272

[8]

[No title captured]

← 1 →