3-D Content Addressable Memory Architectures

被引：4

作者：

Hu, Yong-Jyun ^{[1
]}

Li, Jin-Fu ^{[1
]}

Huang, Yu-Jen ^{[1
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Adv Reliable Syst ARES Lab, Jhongli 320, Taiwan

来源：

2009 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING, PROCEEDINGS | 2009年

关键词：

INTEGRATED-CIRCUITS; SILICON;

D O I：

10.1109/MTDT.2009.20

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Three-dimensional (3-D) integration is an emerging integrated circuit technology. Semiconductor memory is very suitable to be realized using 3-D technology due to its regularity. Different from random access memories (RAMs), a content addressable memory (CAM) has a priority address encoder (PAE) for evaluating the comparison result. The existing of PAE causes that the design of 3-D architectures for CAMs is more difficult than that for RAMs. This paper proposes a matchline-partitioned 3-D architecture and a searchline-partitioned 3-D architectures for CAMs. An inter-layer interleaving scheme is proposed to distribute PAE logic circuits evenly in two layers such that the footprint of a 3-D CAM is minimized. Experimental results show that the proposed 3-D CAM have better search performance for most of CAMs used in the industry.

引用

页码：59 / 64

页数：6

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