Low Delay Based 4 Bit QSD Adder/Subtraction Number System By Reversible Logic Gate

被引：0

作者：

Agarwal, Purva ^{[1
]}

Whig, Pawan ^{[1
]}

机构：

[1] RIET, Jaipur, Rajasthan, India

来源：

2016 8TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS (CICN) | 2016年

关键词：

Carry free addition; Fast computing; FPGA; Quaternary Signed Digit; VHDL; VLSI;

D O I：

10.1109/CICN.2016.119

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In the Modern computers for performing the operation of ALU (Arithmetic Logic Unit) like Addition, Subtraction, different types of adders are using for achieving low delay and fast output. QSD numbers are using for giving the carry-free addition so that ALU operations can perform in low delay and speed of the modern computer can increase. In the modern digital system fast adder, Subtraction can perform by use QSD numbers. The range of QSD numbers is -3 to +3. In this paper, we are performing the 4 Bit QSD Addition and subtraction by Reversible Logic Gate based Full adder. For performing fast operation, we are also introducing Pipelining so that delay can be further reduced in the process of addition and subtraction. As we can see from the results session, the delay get reduce up to 92 % by apply Reversible Logic Gate based full adder with Pipelining.

引用

页码：580 / 584

页数：5