Low power and high performance clock delayed domino logic using saturated keeper

被引：4

作者：

Amirabadi, A. ^{[1
]}

Chehelcheraghi, A.

Rasouli, S. H.

Seyedi, A.

Afzai-Kusha, A.

机构：

[1] Univ Tehran, Dept Elect Commun Engn, Low Power High Performance Nanosyst Lab, Tehran, Iran

[2] Shahid Beheshti Univ, Dept Elect & Comp Engn, Tehran, Iran

来源：

2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/ISCAS.2006.1693299

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this work, domino logic with a saturated keeper technique is proposed. The circuit, which is used to implement the technique, is as simple as the utilized NOT gate in standard domino. By using the simple structure, we can obtain better performance, noise immunity, and lower power consumption. The simulation results for a 70 nm CMOS technology show an improvement between 7% and 62.5% in delay and 9% and 14% in power consumption, over its previous suggestions.

引用

页码：3173 / 3176

页数：4

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