Transistor optimization for leakage power management in a 65nm CMOS technology for wireless and mobile applications

被引：0

作者：

Zhao, S ^{[1
]}

Chatterjee, A ^{[1
]}

Tang, S ^{[1
]}

Yoon, J ^{[1
]}

Crank, S ^{[1
]}

Bu, H ^{[1
]}

Houston, T ^{[1
]}

Sadra, K ^{[1
]}

Jain, A ^{[1
]}

Wang, Y ^{[1
]}

Redwine, D ^{[1
]}

Chen, Y ^{[1
]}

Siddiqui, S ^{[1
]}

Zhang, G ^{[1
]}

Laaksonen, T ^{[1
]}

Hall, C ^{[1
]}

Chang, S ^{[1
]}

Olsen, L ^{[1
]}

Riley, T ^{[1
]}

Meek, C ^{[1
]}

Hossain, I ^{[1
]}

Rosal, J ^{[1
]}

Tsao, A ^{[1
]}

Wu, J ^{[1
]}

Scott, D ^{[1
]}

机构：

[1] Texas Instruments Inc, Silicon Tech Dev, Dallas, TX 75243 USA

来源：

2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a transistor optimization methodology tailored for wireless, digital consumer, and mobile applications that employ power management circuit techniques. This methodology is applied to a 65nm technology that supports a high-density (<0.5um(2)) embedded 6T SRAM cell. High performance logic (I-dn/l(dp) = 550/300uA/um at L-poly = 39nm) and low leakage are achieved simultaneously by employing a data retention mode for the SRAM (I-1eakage,similar to2pA/bit). Retention mode bias conditions and selective gate sizing in the SRAM reduces leakage by similar to300X. Advanced transistor design including SSR channel, strain engineering, drain-extension (HDD) offset spacer, and HDD and halo profile optimization is used to achieve at least an additional 4X reduction in leakage.

引用

页码：14 / 15

页数：2