40Gbit/s fully monolithic clock recovery IC using InAlAs/InGaAs/InP HEMTs

被引：8

作者：

Murata, K

Yamane, Y

机构：

[1] Nippon Telegraph & Tel Corp, Network Innovat Labs, Kanagawa 2390847, Japan

[2] Nippon Telegraph & Tel Corp, Photon Labs, Atsugi, Kanagawa 2430124, Japan

来源：

ELECTRONICS LETTERS | 2000年 / 36卷 / 19期

关键词：

D O I：

10.1049/el:20001163

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The authors describe a 40Gbit/s fully monolithic clock recovery integrated circuit (IC) fabricated using 0.1 mu m InAlAs/InGaAs/InP HEMTs. The IC utilises injection locking, and consists of a half bit delay, an exclusive OR gate and a T-type flip-flop. The IC extracts a half-rate clock signal from a 39.81312Gbit/s 2(31) - 1 pseudo-random bit sequence signal without any other external components.

引用

收藏

页码：1617 / 1618

页数：2

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