Decapsulation Method for 3D Stacked-die Packaged Devices

被引：0

作者：

Lin, Xiaoling ^{[1
,2
]}

Liang, Chaohui ^{[2
]}

机构：

[1] MIIT, Inst 5, Sci & Technol Lab Reliabil Phys & Applicat Elect, Guangzhou, Peoples R China

[2] MIIT, Inst 5, Reliabil Anal Ctr, Guangzhou, Peoples R China

来源：

2020 IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA) | 2020年

关键词：

3D stacked-die package; MEMS inertial devices; decapsulation; inspection;

D O I：

10.1109/ipfa49335.2020.9260867

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

3-dimensional (3D) stacked-die package is one of the important package styles for MEMS inertial devices. Its unique packaging brings new challenges for its decapsulation method. In this paper, a new decapsulation method for 3D stacked-die packaged MEMS inertial devices is introduced with method's steps, technical flow and application. This decapsulation method is the combination of laser-decap and multi-steps chemical etching. It reveals the stacked-dies layer by layer and makes the possibility to analyze the structures in the MEMS inertial devices, such as accelerometer, gyroscope, ASIC, etc. It provides good technical support for inner-inspection of 3D stacked-die packaged MEMS inertial devices.

引用

页数：5

共 50 条

[41] Design for 3D Stacked Circuits
Franzon, P.
Davis, W.
Rotenberg, E.
Stevens, J.
Lipa, S.
Nigussie, T.
Pan, H.
Baker, L.
Schabel, J.
Dey, S.
Li, W.
2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2021,
[42] Thermal for 3D stacked modules✩
Chen, Yanning
Zhao, Dongyan
Liu, Fang
Gao, Jie
Zhu, Hui
MICROELECTRONICS JOURNAL, 2023, 139
[43] The time is now for 3-D stacked die
Nelson, Rick
EDN, 2010, 55 (13) : 9 - 9
[44] 3-D design of stacked die and SiP
Jensen, G. (gjensen@cad-design.com), 2005, IHS Publishing Group (14):
[45] 3-D Stacked Die: Now or Future?
Bansal, Samta
Rey, Juan C.
Yang, Andrew
Jang, Myung-Soo
Lu, L. C.
Magarshack, Philippe
Pol, Marchal
Radojcic, Riko
PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 298 - 299
[46] Mechanical effects of copper through-vias in a 3D die-stacked module
Tanaka, N
Sato, T
Yamaji, Y
Morifuji, T
Umemoto, M
Takahashi, K
52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS, 2002, : 473 - +
[47] 3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding
Katti, G.
Mercha, A.
Van Olmen, J.
Huyghebaert, C.
Jourdain, A.
Stucchi, M.
Rakowski, M.
Debusschere, I.
Soussan, P.
Dehaene, W.
De Meyer, K.
Travaly, Y.
Beyne, E.
Biesemans, S.
Swinnen, B.
2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 331 - 334
[48] Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit
Melamed, Samson
Imura, Fumito
Nakagawa, Hiroshi
Kikuchi, Katsuya
Hagimoto, Michiya
Matsumoto, Yukoh
Aoyagi, Masahiro
MICROELECTRONICS JOURNAL, 2015, 46 (12) : 1106 - 1113
[49] Direct Concentration Approach of Moisture Diffusion and Whole-Field Vapor Pressure Modeling for Reflow Process-Part II: Application to 3D Ultrathin Stacked-Die Chip Scale Packages
Xie, B.
Fan, X. J.
Shi, X. Q.
Ding, H.
JOURNAL OF ELECTRONIC PACKAGING, 2009, 131 (03) : 0310111 - 0310116
[50] Functional Testing of AI Cores through Thinned 3D I/O Buffer Dies in 3D Die-Stacked Modules
Farooq, Mukta
Kumar, Arvind
Lee, Sae-Kyu
Bonam, Ravi
Gomez, Juan-Manuel
Kelly, James
Hosokawa, Kohji
Nomura, Akiyo
Kohda, Yasuteru
Dickson, Timothy
Sakuma, Katsuyuki
Mori, Hiroyuki
Rubin, Joshua
Saraf, Iqbal
Pai, Vinay
Nieves, Pablo
Li, Yandong
DelaPena, Abraham
Wassick, Thomas
Perfecto, Eric
Carr, Christopher
Sardesai, Viraj
Miller, Eric
Oakley, Jennifer
Skordas, Spyridon
Teehan, Sean
McHerron, Dale
Burns, Jeff
Divakaruni, Rama
IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022), 2022, : 977 - 980

← 1 2 3 4 5 →