Decapsulation Method for 3D Stacked-die Packaged Devices

被引:0
|
作者
Lin, Xiaoling [1 ,2 ]
Liang, Chaohui [2 ]
机构
[1] MIIT, Inst 5, Sci & Technol Lab Reliabil Phys & Applicat Elect, Guangzhou, Peoples R China
[2] MIIT, Inst 5, Reliabil Anal Ctr, Guangzhou, Peoples R China
关键词
3D stacked-die package; MEMS inertial devices; decapsulation; inspection;
D O I
10.1109/ipfa49335.2020.9260867
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
3-dimensional (3D) stacked-die package is one of the important package styles for MEMS inertial devices. Its unique packaging brings new challenges for its decapsulation method. In this paper, a new decapsulation method for 3D stacked-die packaged MEMS inertial devices is introduced with method's steps, technical flow and application. This decapsulation method is the combination of laser-decap and multi-steps chemical etching. It reveals the stacked-dies layer by layer and makes the possibility to analyze the structures in the MEMS inertial devices, such as accelerometer, gyroscope, ASIC, etc. It provides good technical support for inner-inspection of 3D stacked-die packaged MEMS inertial devices.
引用
收藏
页数:5
相关论文
共 50 条
  • [21] Effects of 3D Via and Die Attach on Power Integrity of a Packaged IC
    Lin, Yi-Chieh
    Lin, Yu-Chih
    Horng, T. -S.
    Hwang, Lih-Tyng
    2012 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC 2012), 2012, : 277 - 279
  • [22] Effect of die bonding condition for die attach film performance in 3D QFN stacked die
    Jalar, A.
    Rosle, M. F.
    Hamid, M. A. A.
    NEW ASPECTS OF MICROELECTRONICS, NANOELECTRONICS, OPTOELECTRONICS, 2008, : 31 - 35
  • [23] True 3D Packaging Solution for Stacked Vertical Power Devices
    Rouger, N.
    Benaissa, L.
    Widiez, J.
    Imbert, B.
    Gaude, V.
    Verrun, S.
    Crebier, J. C.
    2013 25TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2013, : 97 - 100
  • [24] Thermodynamic Analysis in Failure Analysis of 3D Stacked Package Devices
    Wang, Xu
    Ding, Zhimin
    Duan, Chao
    Meng, Meng
    Liu, Yudong
    Wang, Zhibin
    Yu, Xiangtian
    2021 THE 6TH INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM 2021), 2021, : 137 - 141
  • [25] THE NUMERICAL STUDY FOR THE THERMAL CHARACTERISTICS OF 3D VERTICAL STACKED DIE PACKAGES
    Yu, Chin-Kuang
    Hsieh, Ming-Che
    Liu, Chun-Kai
    Dai, Ming-Ji
    Tain, Ra-Min
    IPACK 2009: PROCEEDINGS OF THE ASME INTERPACK CONFERENCE 2009, VOL 2, 2010, : 507 - 512
  • [26] Sample Preparation for Deprocessing of 3D Multi-Die Stacked Package
    Kor, H. B.
    Liu, Q.
    Gan, C. L.
    2020 IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2020,
  • [27] NUMERICAL AND EXPERIMENTAL DETERMINATION OF TEMPERATURE DISTRIBUTION IN 3D STACKED POWER DEVICES
    Morgan, Adam
    Choobineh, Leila
    Fresne, David
    Hopkins, Douglas C.
    PROCEEDINGS OF THE ASME INTERNATIONAL TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC MICROSYSTEMS, 2017, 2017,
  • [28] Impact of Die-to-Die Thermal Coupling on the Electrical Characteristics of 3D Stacked SRAM Cache
    Chatterjee, Subho
    Cho, Minki
    Rao, Rahul
    Mukhopadhyay, Saibal
    2012 28TH ANNUAL IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM (SEMI-THERM), 2012, : 14 - 19
  • [29] Wafer Level 3D Stacked Technology Solution for Future IoT Devices
    Murayama, Takahide
    Sakuishi, Toshiyuki
    Suzuki, Akiyoshi
    Morikawa, Yasuhiro
    2018 INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING AND IMAPS ALL ASIA CONFERENCE (ICEP-IAAC), 2018, : 23 - 26
  • [30] From Printed Devices to Vertically Stacked, 3D Flexible Hybrid Systems
    Liu, Fengyuan
    Christou, Adamos
    Dahiya, Abhishek Singh
    Dahiya, Ravinder
    ADVANCED MATERIALS, 2025,