The Analysis of Logic Resynthesis Methods to Increase the Fault Tolerance of Combinational Circuits for Single Failures

The paper discusses the methods for protecting logic elements of combinational circuits from single failures. Until recently, the problem of manufacturing the microelectronic products resistant to single failures of logic elements was relevant mainly in the military and space industries. In these areas, the increased requirements are imposed on the fault tolerance of circuits, since the latter are functioning under the influence of external destabilizing factors. These factors can be heavy charged particles that affect the operation of logic elements and cause their single failures. Due to the solid-state devices scaling, the technological standards for integral circuits design and manufacturing change and the fault tolerance problem becomes relevant for devices of the civilian market, also. The paper proposes a technique for a resynthesis of vulnerable areas of logic combinational circuits. To assess the stability, the logic constraints derived from the resolution method are suggested to use.