Compiler scheduling for STA-processors

被引：5

作者：

Cichon, G ^{[1
]}

Robelly, P ^{[1
]}

Seidel, H ^{[1
]}

Bronzel, M ^{[1
]}

Fettweis, G ^{[1
]}

机构：

[1] Tech Univ Dresden, Vodafone Mobile Commun Chair, D-01062 Dresden, Germany

来源：

INTERNATIONAL CONFERENCE ON PARALLEL COMPUTING IN ELECTRICAL ENGINEERING | 2004年

关键词：

D O I：

10.1109/PCEE.2004.1335587

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents an adaptation of the list scheduling algorithm to generate code for processors of the Synchronous Transfer Architecture (STA) by applying techniques known from RISC and TTA. The proposed scheduling approach is based on informed, deterministic algorithms that can be implemented run-time efficiently. Although the presented compiler prototype does not generate optimized code, it provides a proof-of-concept of the feasibility of the proposed compiler architecture.

引用

页码：45 / 50

页数：6