A novel generalized concept for three phase cascaded multilevel inverter topologies

Many new cascaded multilevel inverter (MLI) topologies have recently been proposed and published in the literature. All proposed topologies demand significant amount of semiconductor components and input dc supplies, which is considered the main drawback for the implementation of three phase cascaded MLIs. This paper proposes a new generalized concept that could be employed within any existing cascaded MLI topology in order to reduce its size in terms of device count including semiconductor switches, diodes, and dc power supplies. The new generalized concept involves two stages namely; cascaded stage (CS) and phase generator stage (PGS). The PGS stage is a combination of conventional three phase two level inverter (CTPTLI) and three bidirectional (BD) switches, while the cascaded stage can be modified using any existing cascaded topology. The proposed concept is validated through extensive simulation and experimental analyses. Results show the capability of the proposed technique in reducing device count of the existing topologies while maintaining its performance.