Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review

被引：5
作者：
Guo, Mingqiang [1 ,2 ]
Sin, Sai-Weng [1 ,2 ]
Qi, Liang [3 ]
Xu, Dengke [4 ]
Wang, Guoxing [3 ]
Martins, Rui P. [1 ,2 ,5 ]
机构：
[1] Univ Macau, Inst Microelect, State Key Lab Analog & Mixed Signal VLSI, Macau, Peoples R China
[2] Univ Macau, FST ECE, Macau, Peoples R China
[3] Shanghai Jiao Tong Univ, Dept Micro Nano Elect, Shanghai 200240, Peoples R China
[4] Amicro Semicond Co Ltd, Zhuhai 519000, Peoples R China
[5] Univ Lisbon, Inst Super Tecn, P-1049001 Lisbon, Portugal
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2022年 / 69卷 / 06期
基金：
国家重点研发计划;
关键词：
Timing; Calibration; Bandwidth; Very large scale integration; Finite impulse response filters; Clocks; Tuning; Time-interleaved; ADC; timing mismatch; background; calibration; SAR ADC; SKEW; BANDWIDTH;
D O I：
10.1109/TCSII.2022.3160736
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This brief presents an overview of recent background timing mismatch calibration techniques in time-interleaved ADCs. Regarding the methods of detecting timing skew, the brief divides the existing methods into two categories: a) strategies based on deterministic equalization and b) techniques based on the statistical information of the input signal. Similarly, we can also divide timing skew correction into analog tuning and digital processing. The brief reviews previous works comparatively with these different methods and summarizes their pros and cons.
引用
收藏
页码：2564 / 2569
页数：6
相关论文
共 45 条
[1]  
[Anonymous], ISSCC 2002 IEEE INT
[2]   Generalized Method for Extraction of Offset, Gain, and Timing Skew Errors in Time-Interleaved ADCs [J].
Azizian, Sarkis ;
Ehsanian, Mehdi .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67 (07) :1214-1218
[3]   High-Speed Time Interleaved ADCs [J].
Buchwald, Aaron .
IEEE COMMUNICATIONS MAGAZINE, 2016, 54 (04) :71-77
[4]   A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration [J].
Chang, Dong-Jin ;
Choi, Michael ;
Ryu, Seung-Tak .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56 (09) :2691-2700
[5]   Least mean square adaptive digital background calibration of pipelined analog-to-digital converters [J].
Chiu, Y ;
Tsang, CW ;
Nikolic, B ;
Gray, PR .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2004, 51 (01) :38-46
[6]   Equalization Techniques for Nonlinear Analog Circuits [J].
Chiu, Yun .
IEEE COMMUNICATIONS MAGAZINE, 2011, 49 (04) :132-139
[7]   General analysis on the impact of phase-skew in time-interleaved ADCs [J].
El-Chammas, Manar ;
Murmann, Boris .
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, :17-20
[8]   A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration [J].
El-Chammas, Manar ;
Murmann, Boris .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (04) :838-847
[9]   A 12-GS/s81-mW 5-bit Time-Interleaved Flash ADC with Background Timing Skew Calibration [J].
El-Chammas, Manar ;
Murmann, Boris .
2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2010, :157-158
[10]   General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs [J].
El-Chammas, Manar ;
Murmann, Boris .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56 (05) :902-910
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