共 70 条
[1]
[Anonymous], 1975, ELECT DEVICES M
[2]
ARGHAVANI R, IN PRESS T ELECT DEV
[3]
ASSADERAGHI F, 2000, P IEEE INT SOI C, P6
[4]
STABILIZATION OF SILICON SURFACES BY THERMALLY GROWN OXIDES
[J].
BELL SYSTEM TECHNICAL JOURNAL,
1959, 38 (03)
:749-783
[6]
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell
[J].
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST,
2004,
:657-660
[7]
BALK P, 1965, ELECTROCHEM SOC SPRI
[8]
Electron transport in a model Si transistor
[J].
SOLID-STATE ELECTRONICS,
2000, 44 (09)
:1689-1695
[9]
BARLAGE D, 2001, INT EL DEV M