The hardware implementation of a genetic algorithm model with FPGA

被引：3
|
作者：
Tu, L [1 ]
Zhu, MC [1 ]
Wang, JX [1 ]
机构：
[1] Shenzhen Univ, EDA Technol Ctr, Shenzhen 518060, Peoples R China
来源：
2002 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS | 2002年
关键词：
genetic algorithm (GA); FPGA; hardware implementation;
D O I：
10.1109/FPT.2002.1188714
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A genetic algorithm (GA) is a robust parallel calculation method based on natural selection, which can be applied to the distributed and concentrated industry optimizing control process. The hardware function of GA operation can be implemented by FPGA. In this paper, a hardware implementation method of GA based on FPGA is presented. The results of this research can be applied to the study and implementation of evolvable hardware (EHW).
引用
收藏
页码：374 / 377
页数：4
相关论文
共 50 条
  • [41] FPGA based Hardware Implementation of Hybrid Cryptographic Algorithm for Encryption and Decryption
    Shende, Vikrant
    Kulkarni, Meghana
    2017 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, COMMUNICATION, COMPUTER, AND OPTIMIZATION TECHNIQUES (ICEECCOT), 2017, : 416 - 419
  • [42] Reconfigurable hardware implementation of K-nearest neighbor algorithm on FPGA
    Yacoub, Mohammed H.
    Ismail, Samar M.
    Said, Lobna A.
    Madian, Ahmed H.
    Radwan, Ahmed G.
    AEU - International Journal of Electronics and Communications, 2024, 173
  • [43] Hardware implementation of a background substraction algorithm in FPGA-based platforms
    Calvo-Gallego, Elisa
    Sanchez-Solano, Santiago
    Brox Jimenez, Piedad
    2015 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT), 2015, : 1688 - 1693
  • [44] A FPGA implementation of a self-adaptive genetic algorithm
    Thirer, Nonel
    ARTIFICIAL INTELLIGENCE AND MACHINE LEARNING FOR MULTI-DOMAIN OPERATIONS APPLICATIONS II, 2020, 11413
  • [45] Implementation of a biologically realistic spiking neuron model on FPGA hardware
    Glackin, B
    Maguire, LP
    McGinnity, TM
    Belatreche, A
    Wu, Q
    Proceedings of the 8th Joint Conference on Information Sciences, Vols 1-3, 2005, : 1412 - 1415
  • [46] A novel pipeline based FPGA implementation of a genetic algorithm
    Thirer, Nonel
    MACHINE INTELLIGENCE AND BIO-INSPIRED COMPUTATION: THEORY AND APPLICATIONS VIII, 2014, 9119
  • [47] FPGA implementation of a ridge extraction fingerprint algorithm based on microblaze and hardware coprocessor
    Lopez-Garcia, Mariano
    Navarro, Enrique F. Canto
    2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2006, : 79 - 83
  • [48] TERO-Based Detection of Hardware Trojans on FPGA Implementation of the AES Algorithm
    Digital IC DEsign and Systems Laboratory , Computer and Informatics Engineering Department, TEI of Western Greece, Greece
    不详
    Proc. - Euromicro Conf. Digit. Syst. Des., DSD, (678-681):
  • [49] TERO-based Detection of Hardware Trojans on FPGA Implementation of the AES Algorithm
    Kitsos, Paris
    Stefanidis, Kyriakos
    Voyiatzis, Artemios G.
    19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016), 2016, : 678 - 681
  • [50] An improved non-uniformity correction algorithm and its hardware implementation on FPGA
    Rong Shenghui
    Zhou Huixin
    Wen Zhigang
    Qin Hanlin
    Qian Kun
    Cheng Kuanhong
    INFRARED PHYSICS & TECHNOLOGY, 2017, 85 : 410 - 420
12345