Design for test technique for increasing the resolution of supply current monitoring in analogue circuits

被引：3

作者：

Chalk, CD ^{[1
]}

Zwolinski, M ^{[1
]}

机构：

[1] Univ Southampton, Dept Elect & Comp Sci, Southampton SO17 1BJ, Hants, England

来源：

ELECTRONICS LETTERS | 1997年 / 33卷 / 21期

关键词：

design for testability; circuit testing;

D O I：

10.1049/el:19971174

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A design-for-test (DFT) technique for analogue circuits is proposed which splits all high current transistors into two. This technique reduces the fault-masking effects of the fault-free parts of the circuit, giving a potential fault cover of over 99%. Other advantages are the small area overhead and a low performance penalty.

引用

页码：1746 / 1748

页数：3

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