Finite-Impulse-Response (FIR) Feedback in Continuous-Time Delta-Sigma Converters

被引:0
作者
Pavan, Shanthi [1 ]
机构
[1] Indian Inst Technol, Madras, Tamil Nadu, India
来源
2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2018年
关键词
CLOCK JITTER; MODULATOR; COMPENSATION; DESIGN; ADC;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Finite-impulse-response (FIR) feedback was originally introduced as a way to address the problem of loop-filter nonlinearity and clock jitter in continuous-time delta-sigma modulators. It turns out that FIR feedback has other benefits it reduces the effect of the quantizer's data-dependent jitter and enables the use of chopping "for free". It is an architectural technique that combines the benefits of single-bit and multibit operation, and has proven itself to be robust and scalable, applicable to Delta Sigma data converters targeting a variety of specifications, and across process nodes. This paper reviews the key challenges encountered in the design of high performance delta-sigma data converters, and describes the role of FIR feedback in addressing these challenges. The prospect of using FIR feedback to achieve wide bandwidths is examined, and promising directions are reviewed.
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页数:8
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