Low power current-mode binary-tree asynchronous Min/Max circuit

被引:20
作者
Dlugosz, Rafal [1 ]
Talaska, Tomasz [2 ]
机构
[1] Swiss Fed Inst Technol Lausanne, Inst Microtechnol, CH-2000 Neuchatel, Switzerland
[2] Univ Technol & Life Sci, Fac Telecommun & Elect Engn, PL-85796 Bydgoszcz, Poland
关键词
Min/Max circuits; Current-mode; Asynchronous circuits; Parallel data processing; Kohonen neural networks; Nonlinear filters; TAKE-ALL CIRCUIT; HIGH-SPEED; MISMATCH; NETWORK;
D O I
10.1016/j.mejo.2009.12.009
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel, current-mode, binary-tree, asynchronous Min/Max circuit for application in nonlinear filters as well as in analog artificial neural networks is proposed. The relatively high precision above 99% can be achieved by eliminating the copying of the input signals from one layer to the other in the tree. In the proposed solution, the input signals are always directly copied to particular layers using separate signal paths. This makes the precision almost independent on the number of the layers i.e. the number of the inputs. The circuit is a flexible solution. The power dissipation, as well as data rate can be scaled up and down in a wide range. For an average value of the input currents of 20 mu A and data rate of 11 MHz the circuit dissipates 505 mu W, while for the signals of 200 nA and data rate of 500 kHz the power dissipation is reduced to 1 mu W. The prototype circuit with four inputs, realized in the CMOS 0.18 mu m technology, occupies the area of 1800 mu m(2). (c) 2009 Elsevier Ltd. All rights reserved,
引用
收藏
页码:64 / 73
页数:10
相关论文
共 33 条
[31]  
WILAMOWSKI BM, 2000, NASA S VLSI DES
[32]   Design of high performance CMOS current-mode winner-take-all circuit [J].
Yu, CC ;
Tang, YC ;
Liu, BD .
2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, :568-572
[33]   Bi-directional current-mode multiple input maximum circuit [J].
Yu, GJ ;
Liu, BD ;
Huang, CY .
PROCEEDINGS OF THE SECOND IEEE ASIA PACIFIC CONFERENCE ON ASICS, 2000, :41-44