STEM: A Scheme for Two-Phase Evaluation of Majority Logic

被引:2
作者
Mankalale, Meghna G. [1 ]
Liang, Zhaoxin [1 ]
Sapatnekar, Sachin S. [1 ]
机构
[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA
关键词
All-spin logic; majority logic; spintronics; two-phase logic; DEVICES;
D O I
10.1109/TNANO.2017.2695641
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The switching time of a magnet in a spin-currentbased majority gate depends on the input vector combination, and this often restricts the speed of majority-based circuits. To address this issue, this work proposes a novel two-phase scheme to implement majority logic and evaluates it on an all-spin logic (ASL) majority-based logic structures. In Phase 1, the output is initialized to a preset value. Next, in Phase 2, the inputs are evaluated to switch the output magnet to its correct value. The time window for the output to switch in Phase 2 is fixed. Using such a scheme, an n-input AND gate that requires a total of (2n - 1) inputs in the conventional implementation can now be implemented with only (n + 1) inputs. When applied to standard logic functions, it is demonstrated that the proposed method of designing ASL gates is 1.6-3.4x faster and 1.9-6.9x more energy efficient than the conventional method, and for a five-magnet full adder, it is shown that the proposed ASL implementation is 1.5x faster, 2.2x more energy efficient, and provides a 16% improvement in area.
引用
收藏
页码:606 / 615
页数:10
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