Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

被引:4
作者
de Souza, Michelly [1 ]
Barraud, Sylvain [2 ]
Casse, Mikael
Vinet, Maud [2 ]
Faynot, Olivier [2 ]
Pavanello, Marcelo Antonio [1 ]
机构
[1] Ctr Univ FEI, Dept Elect Engn, Sao Bernardo Do Campo, SP, Brazil
[2] Univ Grenoble Alpes, CEA Leti, MINATEC Campus, Grenoble, France
来源
IEEE 51ST EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2021) | 2021年
基金
巴西圣保罗研究基金会;
关键词
junctionless transistor; nanowire transistor; variability; matching; electrical characterization; MODEL;
D O I
10.1109/ESSDERC53440.2021.9631827
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, experimental assessment of the variability of threshold voltage and drain current in junctionless nanowire nMOS transistors is presented. Die-to-die variability of threshold voltage and drain current is presented and compared to inversion mode nanowire with the same dimensions. Although the junctionless nanowires have shown larger threshold voltage matching coefficients than inversion mode devices, the variability obtained experimentally has shown to be smaller than predicted by some simulations reported in the literature. Also, it has been shown that as the channel length of junctionless nanowire transistors is reduced, the current variability becomes smaller than in inversion mode nanowires, at the same current level and dimensions.
引用
收藏
页码:223 / 226
页数:4
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