Direct evaluation of gate line edge roughness impact on extension profiles in sub-50nm N-MOSFETs

被引：7

作者：

Fukutome, H ^{[1
]}

Momiyama, Y ^{[1
]}

Kubo, T ^{[1
]}

Tagawa, Y ^{[1
]}

Aoyama, T ^{[1
]}

Arimoto, H ^{[1
]}

机构：

[1] Fujitsu Labs Ltd, Tokyo 1970833, Japan

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | 2004年

关键词：

D O I：

10.1109/IEDM.2004.1419179

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We directly evaluated the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-FETs. Using scanning tunneling microscopy, we clearly observed that the roughness of the extension edges induced by the gate LER strongly depended on the implanted dose, pockets, and co-implantations. Impurity diffusion suppressed by a nitrogen (N) co-implant enhanced the roughness of the extension edges, which caused fluctuation in the device performance. We verified the expected impact of the N co-implant on the electrical performance of the n-FETs.

引用

页码：433 / 436

页数：4

共 7 条

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