Thermal optimization of IGBT modules based on finite element method and particle swarm optimization

Power modules have thermal stresses, and alternatives to the present methods are needed to identify the chips' optimal position. By applying an optimization technique in the design process, the entire module will produce lower junction temperature, but methods based on trial and error as well as mathematical models may not provide an accurate result. This paper reveals a combined approach based on the finite element method and the particle swarm optimization algorithm to determine the ideal position of the chips within an insulated-gate bipolar transistor module in terms of junction temperature. Three scenarios are examined to cover all possible positions. The first scenario allows each chip to move asymmetrically and is selected as the most efficient situation of the chips. The preferred situation will result in a lower junction temperature and decreases the overall temperature approximately 25 degrees K.