High-speed receivers for on-chip interconnections in deep-submicron process

被引：0

作者：

Huang, HY ^{[1
]}

Chen, SL ^{[1
]}

机构：

[1] Fu Jen Catholic Univ, Dept Elect Engn, VLSI CAD Lab, Taipei, Taiwan

来源：

ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The transient sensitive trigger (TST) was used to improve the RC delay time of the long interconnection in deep sub-micron process. The conventional TST circuit has a threshold voltage drop during the transitions which results in a longer delay time. In this work, the modified techniques are proposed to improve the drawback of the conventional TST. The new versions have 45-74% delay improvement compared to the conventional TST simulated using a 0.25mum CMOS process. The proposed circuits can be applied to the receiving of long interconnection signal for the applications of high-speed VLSI.

引用

页码：769 / 772

页数：4

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