Dead-time Compensation and Realization Method for 3-Level NPC Inverter

被引：0

作者：

Hong, Seok-Jin ^{[1
]}

Shin, Soo-Cheol ^{[2
]}

Kim, Hak-Sung ^{[3
]}

Won, Chung-Yuen ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Suwon, South Korea

[2] LG Elect, In Cheon, South Korea

[3] Dongyang Mirea Univ, Gu Ro, South Korea

来源：

2014 IEEE TRANSPORTATION ELECTRIFICATION CONFERENCE AND EXPO (ITEC) ASIA-PACIFIC 2014 | 2014年

关键词：

Dead-time; Compensation; 3-Level NPC Inverter; Compensation Method; Deadtime Compensation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

3-Level Neutral Point Clamped (NPC) Inverter has 4 switches in each leg. 2 pairs of switches of the inverter operate complimentarily, Si and S3 is a pair, the other is S2 and S4. But short circuit fault can be occurred due to a time distinction of turning on/off the switch. Thus, short circuit fault can be prevented by giving dead-time when turning on the switches which complementarily operate mutually. But these dead-time occur error between reference voltage and output voltage of each leg, and distort 3-phase output voltage and current. In this paper, a compensation method and its simple realizing method are proposed to minimize effect from these dead-time. The proposed method is implemented on software and does not require an additional hardware. The proposed method is applied to 3-Level NPC inverter and verified its validity through simulation.

引用

页数：5

共 10 条

[1]

[Anonymous], POWER ELECT IEEE T, V14, P782

[2]

[Anonymous], IEEE T, V14, P782

[3]

Horie A, 1995, P IEE JAP IAS ANN RE, P75

[4]

Mese H, 2011, INTERNATIONAL AEGEAN CONFERENCE ON ELECTRICAL MACHINES AND POWER ELECTRONICS & ELECTROMOTION JOINT CONFERENCE, P101, DOI 10.1109/ACEMP.2011.6490577

[5]

Nabae Akira, 1981, IND APPL IEEE T, VIA-17

[6]

Osawa C, 1997, PROCEEDINGS OF THE POWER CONVERSION CONFERENCE - NAGAOKA 1997, VOLS I AND II, P225, DOI 10.1109/PCCON.1997.645616

[7] Pulse-based dead-time compensation method for self-balancing space vector pulse width-modulated scheme used in a three-level inverter-fed induction motor drive [J].

Patel, P. J. ;

Patel, Vinod ;

Tekwani, P. N. .

IET POWER ELECTRONICS, 2011, 4 (06) :624-631

[8]

Song JH, 1997, ISIE '97 - PROCEEDINGS OF THE IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, VOLS 1-3, P283, DOI 10.1109/ISIE.1997.648951

[9]

Yamanaka K, IND APPL C 2001 36 I, V2, P851

[10]

YAZDANI A, 2005, THESIS U TORONTO

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