Line Width Roughness mitigation in chemically amplified resist by post-litho processes

被引:15
作者
Pret, Alessandro Vaglio [1 ]
Gronheid, Roel [1 ]
机构
[1] IMEC VZW, B-3001 Louvain, Belgium
关键词
LWR; Post-litho processes; Smoothing techniques; PSD; EDGE;
D O I
10.1016/j.mee.2009.11.038
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In order to reach and control the ITRS 3 sigma Line Width Roughness target for the 22 nm technological node, post-litho smoothing processes have been studied. To obtain a full knowledge of the roughness response to these techniques, a detailed methodological analysis in both spatial and frequency domain was performed to find the optimum settings. Furthermore, an on-line metrological study on CD-SEM parameters was executed to establish the repeatability of roughness evaluations: 0.2-0.3 nm 3 sigma roughness was in the end found. To validate our methodology, a complete off-line analysis of in-track Hard Bake smoothing process was performed. Up to 11% roughness mitigation in the high frequency range was found. (C) 2009 Elsevier B.V. All rights reserved.
引用
收藏
页码:1127 / 1130
页数:4
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