Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing

被引:0
作者
Moiseev, Konstantin [1 ]
Wimer, Shmuel [2 ]
Kolodny, Avinoam [1 ]
机构
[1] Technion Israel Inst Technol, Dept Elect Engn, IL-32000 Haifa, Israel
[2] Intel Israel 74 Ltd, Mobile Platform Grp, IL-31015 Haifa, Israel
来源
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that cross-capacitances are optimally shared for circuit timing optimization. Using an Elmore delay model including cross capacitances for a bundle of wires, we show that an optimal wire ordering is uniquely determined, such that best timing can be obtained by proper allocation of wire widths and inter-wire spaces. The optimal order, called BMI (Balanced Monotonic Interleaved) depends only on the size of drivers for a wide range of cases. Heuristics are presented for simultaneous ordering, sizing and spacing of wires. Examples for 90-nanometer technology are analyzed and discussed.
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页码:329 / +
页数:2
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