Exploiting Correlation in Stochastic Computing based Deep Neural Networks

Edge Artificial Intelligence or Edge Intelligence, is beginning to receive a tremendous amount of interest. Unfortunately, the incorporation of AI characteristics to edge computing devices presents the drawbacks of being power and area hungry for typical machine learning techniques such as Convolutional Neural Networks (CNN). In this work, we propose a new power-and-area-efficient architecture for implementing Artificial Neural Networks (ANNs) in hardware, based on the exploitation of correlation phenomenon in Stochastic Computing (SC) systems. The architecture proposed can solve the difficult implementation challenges that SC presents for CNN applications, such as the high resources used in binary-to-stochastic conversion, the inaccuracy produced by an undesired correlation between signals, and the stochastic maximum function implementation. Compared with traditional binary logic implementations, experimental results showed an improvement of 19.6x and 63x in terms of speed performance and energy efficiency for the FPGA implementation. For the first time, a fully-parallel CNN as LENET-5 is embedded and tested in a single FPGA, showing the benefits of using stochastic computing for embedded applications, in contrast to traditional binary logic implementations.