Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors

被引：47
作者：
Xu, Hao [1 ]
Abidi, Asad A. [1 ]
机构：
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2017年 / 64卷 / 07期
关键词：
Phase locked loops; bang-bang control; phase noise; oscillators; phase detector; ALL-DIGITAL PLL; FREQUENCY-SYNTHESIZER; LOW-COMPLEXITY; NOISE; JITTER; GAIN; TRANSMITTER; CLOCK;
D O I：
10.1109/TCSI.2017.2679683
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency domain that is complete and self-consistent. It enables the manual design of frequency synthesis PLLs for loop bandwidth, output phase noise and minimum jitter. Tradeoffs between various parameters of the loop become clear. The analysis is validated against measurements on four very different loops, and helps to answer long-standing questions on aspects of these circuits attributable a hard nonlinearity. A brief designer's guide is included.
引用
收藏
页码：1637 / 1650
页数：14
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