Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver

被引：5
|
作者：
Kuboki, Takeshi [1 ]
Tsuchiya, Akira [1 ]
Onodera, Hidetoshi [1 ]
机构：
[1] Kyoto Univ, Dept Commun & Comp Engn, Kyoto 6068501, Japan
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 2007年 / E90C卷 / 06期
关键词：
on-chip signaling; current-mode logic;
D O I：
10.1093/ietele/e90-c.6.1274
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip trans mission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.
引用
收藏
页码：1274 / 1281
页数：8
相关论文
共 50 条
  • [31] Linear low-power 13 GHz SiGe-Bipolar Modulator Driver with 7Vpp differential Output Voltage Swing and on-Chip Bias Tee
    Hettrich, Horst
    Moeller, Michael
    2014 IEEE BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING (BCTM), 2014, : 80 - 83
  • [32] Low-cost low-power self-test design and verification of on-chip ADC for system-on-a-chip applications
    Chandrasekhar, Vivek
    Chen, Chien-In Henry
    Yelamarthi, Kumar
    2006 IEEE INSTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE PROCEEDINGS, VOLS 1-5, 2006, : 1301 - +
  • [33] Low-power CMOS on-chip voltage reference using MOS PTAT: An EP approach
    Seo, YD
    Nam, D
    Yoon, BJ
    Choi, IH
    Kim, B
    TENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS, 1997, : 316 - 320
  • [34] An on-chip instruction cache design with one-bit tag for low-power embedded systems
    Gu, Ji
    Guo, Hui
    Li, Patrick
    MICROPROCESSORS AND MICROSYSTEMS, 2011, 35 (04) : 382 - 391
  • [35] Iris: A Hybrid Nanophotonic Network Design for High-Performance and Low-Power on-Chip Communication
    Li, Zheng
    Mohamed, Moustafa
    Chen, Xi
    Zhou, Hongyu
    Mickelson, Alan
    Shang, Li
    Vachharajani, Manish
    ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2011, 7 (02)
  • [36] Design of power amplifier with on-chip matching circuits using CPW line impedance (K) inverters
    Kanaya, H.
    Pokharel, R. K.
    Kim, S.
    Imada, A.
    Yoshida, K.
    PROCEEDINGS OF THE 11TH WSEAS INTERNATIONAL CONFERENCE ON CIRCUITS, VOL 1: CIRCUITS THEORY AND APPLICATIONS, 2007, : 66 - +
  • [37] Isodelay output driver design using step-wise charging for low power
    Katoch, A
    Veendrick, H
    ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2005, : 149 - 152
  • [38] On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit
    Gu, Jie
    Eom, Hanyong
    Kim, Chris H.
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (06) : 1765 - 1775
  • [39] A LOW-POWER BIPOLAR ECL STANDARD CELL LIBRARY UTILIZING A NOVEL DESIGN METHODOLOGY AND COMPLEMENTARY BIPOLAR DRIVER
    PHAM, P
    KAWAMOTO, E
    DAVIS, G
    SPANGLER, L
    PROCEEDINGS OF THE 1989 BIPOLAR CIRCUITS AND TECHNOLOGY MEETING, 1989, : 19 - 22
  • [40] Clock driver design for low-power high-speed 90-nm CMOS register array
    Enomoto, Tadayoshi
    Nagayama, Suguru
    Shikano, Hiroaki
    Hagiwara, Yousuke
    IEICE TRANSACTIONS ON ELECTRONICS, 2008, E91C (04): : 553 - 561
12345