Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver

被引：5
|
作者：
Kuboki, Takeshi [1 ]
Tsuchiya, Akira [1 ]
Onodera, Hidetoshi [1 ]
机构：
[1] Kyoto Univ, Dept Commun & Comp Engn, Kyoto 6068501, Japan
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 2007年 / E90C卷 / 06期
关键词：
on-chip signaling; current-mode logic;
D O I：
10.1093/ietele/e90-c.6.1274
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip trans mission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.
引用
收藏
页码：1274 / 1281
页数：8
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