Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers

被引：68

作者：

Hsiao, SF ^{[1
]}

Jiang, MR ^{[1
]}

Yeh, JS ^{[1
]}

机构：

[1] Natl Sun Yat Sen Univ, Inst Comp & Informat Engn, Kaohsiung, Taiwan

来源：

ELECTRONICS LETTERS | 1998年 / 34卷 / 04期

关键词：

D O I：

10.1049/el:19980306

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 3-2 counter and a 4-2 compressor are the basic components in the partial product summation tree of a parallel array multiplier. A new high-speed and low power design of these components is presented. Owing to the reduction of the internal load capacitance, the counter and compressor have better speed and power performance than other recently proposed approaches.

引用

页码：341 / 343

页数：3

共 4 条

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