Architecture-aware routability-driven placer for large-scale mixed-size designs

被引:1
作者
Datta, Prasun [1 ]
Mukherjee, Shyamapada [1 ]
机构
[1] Natl Inst Technol Silchar, Dept CSE, Silchar, India
关键词
divide and conquer methods; circuit optimisation; integer programming; integrated circuit layout; network routing; balanced clustering technique; look-ahead legalisation; placement cell; divide conquer strategy; force-directed method; circuit block congestion; pin density; gain-based strategy; routability-driven detailed placement; ICCAD 2012 benchmark circuits; half perimeter wirelength; architecture-aware routability-driven placer; large-scale mixed-size designs; global placement; routing congestion; routability-driven placement; congestion removal approach; site information table; circuit block congestion removal;
D O I
10.1049/iet-cds.2018.5518
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this study, the authors have presented a simple but robust routability-driven placement for the mixed-size designs. The proposed technique is implemented through (i) look-ahead legalisation-based global placement, (ii) congestion removal and (iii) detailed placement stages. A balanced clustering technique has been proposed to group the circuit blocks into clusters based on the types of circuit blocks and their connectivity. A 0-1 integer programming-based global placement method is framed, which performs look-ahead legalisation. A new site information table concept is introduced to keep the information about each placement cell. Based on the divide conquer strategy, placement area is divided into a region to reduce problem size. A force-directed method has been conceived to select an appropriate region for global placement for the blocks of a cluster. A new congestion removal approach substitutes the legalisation stage to remove circuit block congestion and pin density in different regions. Finally, a gain-based strategy has been introduced for routability-driven detailed placement. The proposed technique is implemented and tested on ICCAD 2012 benchmark circuits. It achieves 1.92 and 0.13% improvements in terms of half perimeter wirelength and routing congestion w.r.t. recent placers.
引用
收藏
页码:1209 / 1220
页数:12
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