FPGA implementation of high speed multiplierless frequency response masking FIR filters

被引：6
|
作者：
Lian, Y [1 ]
机构：
[1] Natl Univ Singapore, Dept Elect Engn, Singapore 119260, Singapore
来源：
2000 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION | 2000年
关键词：
D O I：
10.1109/SIPS.2000.886730
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents the design and implementation of high speed, multiplierless, narrow transition width FIR filters using FPGA. The narrow transition width FIR filters are realized by using modified frequency response masking structure which improves the throughput rate by replacing long length filter in the original frequency response masking approach with 2 or 3 cascaded short length filters.
引用
收藏
页码：317 / 325
页数：9
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