Integration of copper PVD and electroplating processes for damascene feature electrofilling

被引：0

作者：

Mayer, S ^{[1
]}

Contolini, R ^{[1
]}

Jackson, R ^{[1
]}

Reid, J ^{[1
]}

Martin, J ^{[1
]}

Morrissey, D ^{[1
]}

Schetty, R ^{[1
]}

机构：

[1] Novellus Syst Inc, Portland Technol Ctr, Wilsonville, OR 97070 USA

来源：

INTERCONNECT AND CONTACT METALLIZATION FOR ULSI | 2000年 / 99卷 / 31期

关键词：

D O I：

暂无

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

The process of manufacturing copper damascene metallization for integrated circuits involves a series of interrelated process steps including dielectric deposition and etching, PVD barrier/seed layer deposition, feature filling by bottom-up electroplating ("electrofilling"), annealing, edge bevel copper removal, and chemical mechanical polishing. In this paper we discuss the interrelationship between the properties of the PVD seed layer, electroplating processes and plating bath additives in achieving void-free electrofill of high aspect ratio structures.

引用

页码：174 / 189

页数：16

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