Fail pattern identification for memory built-in self-repair

With the advent of deep submicron technology and System-on-Chip (SOC) design methodology, we are seeing on-chip memory cores to represent a growing percentage of the chip area. The yield of an SOC is usually dominated by the memory yield, so the improvement of memory yield is crucial in SOC development. In this work, we propose a built-in self-repair (BISR) scheme for memory yield improving. The novelty of our approach is that we can identify the fail patterns so that appropriate spare elements (e.g., spare rows, columns, words, or blocks) can be allocated to repair the defective memory. Some BISR methods are discussed and compared. We select the scheme that uses fewer spare elements than others given the same repair rate. The area overhead of the BISR scheme is only 2.2% for an 8K x 64 memory.