A new full adder cell for low-power applications

被引：17

作者：

Shams, AM ^{[1
]}

Bayoumi, MA ^{[1
]}

机构：

[1] Univ SW Louisiana, Ctr Adv Comp Studies, Lafayette, LA 70504 USA

来源：

PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI | 1998年

关键词：

D O I：

10.1109/GLSV.1998.665198

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new low power CMOS 1-bit full adder cell is presented. It is based on recent design of XOR and XNOR gates [6], and pass-transistors, it has 17 transistors. This cell has been compared to two widely used efficient adder cells; the transmission function full adder cell (16 transistors) [2], and the low power adder cell (14 transistors) [3]. The new cell has no short circuit power and lower dynamic power (than the other adder cells), because of less number and magnitude of circuit capacitances. It consumes 10% to 15% less power than the other two cells. A comparative analysis (using Magic and Hspice) for 8-bit ripple carry and carry select adders shows that the adders based on the new cell can save up to 25% of power consumption.

引用

页码：45 / 49

页数：5