A low-power CMOS nine-channel 40-MHz binary detection system with self-calibrated 500-μV offset

For application in high-energy physics experiments, this paper describes the design of a nine-channel binary detection system featuring a fully differential 300-mu W, 40-MHz comparator whose offset voltage is reduced to less than 500 mu V by means of a digitally controlled calibration system, Besides the comparator, each channel also includes an input waveshaping high-pass filter for improved detection performance in the particle-radiated operating environment. To save area and power, this is realized by a passive snitched-capacitor polyphase network with time-interleaved operation, Two prototype chips have been realized in a 1.2-mu m CMOS technology, One chip includes nine filter-comparator channels that occupy 0.4 mm(2) and at 40 MHz dissipate about 2.7 mW. The other chip contains the calibration system that generates all control signals for offset correction of the filter/comparator channels and occupies 1.4 mm(2).