Reconfigurable MPB Combined with Cache Coherence Protocol in Many-core

Data sharing is an important problem for manycore processor. Penalties of cache misses increase heavily on a larger NoC. In order to address the problem of coherence wall, message passing is introduced into manycore processors. Different from massive parallel processing (MPP) system, manycore is much more sensitive with on-chip storage. In this paper, we propose a reconfigurable cache system, which could reconfigure cache lines into message passing buffers (MPBs) as is needed. In this way, we could improve utilization of on-chip storage. The penalty of hardware design is low because most of functions are reused from structure and state machine in the original cache coherence protocol. This mechanism could be used in any cache protocols with MOESI state machines. Comparing with separated MPB having 5.26% overhead in hardware costs, simulation shows that RMCC has 11.4% improvements in overall performance. At the meantime, RMCC without 5.26% overhead in SRAMs has the same performance with the separated MPB mechanism.