Co-processor architecture for MPEG-4 video object rendering

The most crucial backend algorithm of the new MPEG-4 standard is the computational expensive rendering of arbitrary shaped video objects to the final video scene. This co-processor architecture presents a solution for the scene rendering of the CCIR 601 video format with an arbitrary number of video objects. For the very high data bandwidth rate a hierarchical memory concept has been implemented. The total size of all rendered objects for one scene may reach two times the size of the CCIR 601 format. Running at 100 MHz clock frequency, the co-processor achieves a peak performance of about two billion multiply-accumulate operations. The co-processor has been designed for a 0,35 mu m CMOS technology. About 60% of the overall area of 52 mm(2) is used for on-chip static memory. The power consumption of the co-processor has been estimated with 1 W.