Towards a VLSI architecture for interpolation-based soft-decision Reed-Solomon decoders

被引：32

作者：

Gross, WJ

Kschischang, FR

Koetter, R

Gulak, PG

机构：

[1] McGill Univ, Dept Elect & Comp Engn, Montreal, PQ H3A 2A7, Canada

[2] Univ Toronto, Edward S Rogers Sr Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada

[3] Univ Illinois, Coordinated Sci Lab, Urbana, IL 61801 USA

来源：

JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2005年 / 39卷 / 1-2期

关键词：

Reed-Solomon decoders; soft-decision decoding; VLSI architectures; list decoding; Sudan's algorithm; Guruswami-Sudan algorithm; Koetter-Vardy algorithm; polynomial interpolation; Hasse derivative;

D O I：

10.1023/B:VLSI.0000047274.68702.8d

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The Koetter-Vardy algorithm is an algebraic soft-decision decoder for Reed-Solomon codes which is based on the Guruswami-Sudan list decoder. There are three main steps: (1) multiplicity calculation, (2) interpolation and (3) root finding. The Koetter-Vardy algorithm seems challenging to implement due to the high cost of interpolation. Motivated by a VLSI implementation viewpoint we propose an improvement to the interpolation algorithm that uses a transformation of the received word to reduce the number of iterations. We show how to reduce the memory requirements and give an efficient VLSI implementation for the Hasse derivative.

引用

页码：93 / 111

页数：19

共 30 条

[1] Computing ideals of points [J].