A 5-GHz Class-F3F2 Power Amplifier with 51% PAE and 21-dBm Output Power on 65nm CMOS

被引：0

作者：

Love, Matthew ^{[1
]}

Thian, Mury ^{[1
]}

Grebennikov, Andrei ^{[2
]}

机构：

[1] Queens Univ Belfast, Belfast, Antrim, North Ireland

[2] Sumitomo Elect Europe Ltd, Elstree, England

来源：

2017 IEEE 18TH WIRELESS AND MICROWAVE TECHNOLOGY CONFERENCE (WAMICON) | 2017年

基金：

英国工程与自然科学研究理事会;

关键词：

Cascode; Class-E3F2; CMOS; driver; finite choke; high efficiency; integrated circuits; Inverse Class-B; planar inductors; power amplifier; switched-mode; MAXIMUM OPERATING FREQUENCY;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The design and simulation of a Class-E3F2 power amplifier using 65nm CMOS technology are detailed in this paper. The Class-EF amplifier combines aspects of the Class-E and-F load networks such as the harmonic terminations from the Class F and the use of a shunt capacitance at the drain in the Class E. A mixed-voltage cascode topology is used for the output stage to enable the use of fast low-voltage transistors with a higher supply voltage. To satisfy the Class-EF conditions the load network is designed to provide a short and open circuit to the second and third harmonic signals, respectively. The driver stage utilizes an Inverse Class-B topology to deliver a half-wave rectified sine to the output stage. The simulated amplifier achieved a power-added efficiency of 5l% and a gain of 26 dB at an output power of 21 dBm. The second and third harmonic components were attenuated to-47.6 dBc and-79.3 dBc, respectively.

引用

页数：4