A 5-GHz Class-F3F2 Power Amplifier with 51% PAE and 21-dBm Output Power on 65nm CMOS

The design and simulation of a Class-E3F2 power amplifier using 65nm CMOS technology are detailed in this paper. The Class-EF amplifier combines aspects of the Class-E and-F load networks such as the harmonic terminations from the Class F and the use of a shunt capacitance at the drain in the Class E. A mixed-voltage cascode topology is used for the output stage to enable the use of fast low-voltage transistors with a higher supply voltage. To satisfy the Class-EF conditions the load network is designed to provide a short and open circuit to the second and third harmonic signals, respectively. The driver stage utilizes an Inverse Class-B topology to deliver a half-wave rectified sine to the output stage. The simulated amplifier achieved a power-added efficiency of 5l% and a gain of 26 dB at an output power of 21 dBm. The second and third harmonic components were attenuated to-47.6 dBc and-79.3 dBc, respectively.