A 2 mW, 50 dB DR, 10 MHz BW 5x Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF

被引：8

作者：

Lee, Inhee ^{[1
,2
,3
]}

Han, Gunhee ^{[4
,5
]}

Chae, Youngcheol ^{[1
,2
]}

机构：

[1] Yonsei Univ, Dept Elect, Seoul 120749, South Korea

[2] Yonsei Univ, Dept Elect Engn, Seoul 120749, South Korea

[3] Univ Michigan, Dept Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA

[4] Yonsei Univ, Yonsei Inst Convergence Technol, Inchon 406840, South Korea

[5] Yonsei Univ, Sch Integrated Technol, Inchon 406840, South Korea

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2015年 / 62卷 / 01期

关键词：

Bandpass Delta Sigma modulator; inverter-based OTA; low power; low voltage; radio receiver; switched-capacitor circuit; time-interleaved ADC; LOW-POWER; ADC; BANDWIDTH; CALIBRATION; VOLTAGE; SNDR; GHZ;

D O I：

10.1109/TCSI.2014.2347234

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 2 mW 50 dB-DR 10 MHz-BW bandpass (BP) delta-sigma (Delta Sigma) modulator for a digital-IF receiver is presented. It is based on a power-efficient time-interleaved (TI) architecture, which uses a recursive loop and a feed-forward topology. To further improve its power-efficiency, the ADC employs inverter-based OTAs with the help of auxiliary inverters for extra gain. A 0.55 mm(2) chip is fabricated in a 0.18 mu m CMOS process. Measurements show that the prototype five-path TI BP Delta Sigma modulator achieves 50 dB DR and 46 dB SNDR with 10 MHz bandwidth at 50 MHz IF while dissipating only 2 mW.

引用

页码：80 / 89

页数：10

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