Experiences with Life-cycle Aware Computer Architecture

被引:0
作者
Oliver, John [1 ]
Geyer, Roland [2 ]
Savage, Alan [2 ]
Chong, Frederic T. [2 ]
Amirtharajah, Rajeevan [3 ]
Akella, Venkatesh [3 ]
机构
[1] Calif Polytech State Univ San Luis Obispo, Dept Elect Engn, San Luis Obispo, CA 93407 USA
[2] Univ Calif Santa Barbara, Santa Barbara, CA 93106 USA
[3] Univ Calif Davis, Davis, CA 95616 USA
关键词
computer architecture; life-cycle analysis; sustainability; education;
D O I
暂无
中图分类号
G40 [教育学];
学科分类号
040101 ; 120403 ;
摘要
The dark side of Moore's Law is our society's insatiable need to constantly upgrade our computing devices. As a result, the typical processor is only used for a fraction of it's expected lifetime, despite the immense cost to produce a processor. While the rapid advance of technology makes silicon obsolete in a few years, we propose that chips should be reused for less demanding computing tasks. This re-use strategy creates a food chain of computing devices which amortizes the energy required to build processors over several computing generations. This paper is structured into two parts. First, we describe a proposed a processor re-use strategy, showing that processor re-use makes sense for low-power, embedded processors. These re-usable processors occupy a design space that requires us to implement flexible and reliable processors. The second part of this paper describes student efforts centered around re-usable processors at California Polytechnic State University, San Luis Obispo as well as the University of California, Santa Barbara.
引用
收藏
页码:297 / 304
页数:8
相关论文
共 21 条
[1]   DIVA: A reliable substrate for deep submicron microarchitecture design [J].
Austin, TM .
32ND ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, (MICRO-32), PROCEEDINGS, 1999, :196-207
[2]  
BLOME J, 2006, 2 WORKSH ARCH REL WA
[3]   Life cycle inventory of a CMOS chip [J].
Boyd, Sarah ;
Dornfeld, David ;
Krishnan, Nikhil .
PROCEEDINGS OF THE 2006 IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONICS & THE ENVIRONMENT, CONFERENCE RECORD, 2006, :253-+
[4]   Dynamic thermal management for high-performance microprocessors [J].
Brooks, D ;
Martonosi, M .
HPCA: SEVENTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTING ARCHITECTURE, PROCEEDINGS, 2001, :171-182
[5]  
CLARK LT, 2002, P 2002 INT S LOW POW, P712
[6]  
COURTNEY J, 2006, SW TEST WORKSH
[7]  
Ernst D., 2003, PROC INT S MICROARCH, P7
[8]  
FRANCO P, 1994, P 12 IEEE VLSI TEST
[9]  
Heo S, 2003, ISLPED'03: PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P217
[10]  
ITRS, 2005, SYST DRIV